EDN

System Compiler Adds Support for Mixed-Language Simulation with Verilog and VHDL

San Jose, CA – February 20, 2001 – C Level Design, Inc. today announced a fully automated Verilog Programming Language Interface (PLI) and VHDL Foreign Language Interface (FLI) code generators to ...
EDN

The VHDL and Verilog story

I put a blog entry up on the Oasys blog about their new release, which is the first to support VHDL. But a couple of people told me it was a nice recounting of history so I decided to put a more ...
Electronic Design

VHDL/Verilog Simulator Shows 300% Speed Improvement

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...
Design-Reuse

Hitachi Endorses Model Technology ModelSim for Verilog Simulation

PORTLAND, Ore.--(BUSINESS WIRE)--Oct. 3, 2001--Model Technology(TM), a Mentor Graphics company, today announced that the ModelSim® hardware description language (HDL) simulator has received Verilog ...
Electronics Weekly

VHDL/Verilog training comes with free development board

Esperan is running its project-based HDL training courses through June and July. The aim, says the training company, is to allow designers to implement their project in hardware using supplied ...
CU Boulder News & Events

ECEA 5361 Hardware Description Languages for FPGA Design

This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use ...
Electronic Design

Q&A with Verific’s Rob Dekker on Parsers, Elaborators

Rob Dekker is CTO and Founder of Verific Design Automation. Rob Dekker’s involvement in logic synthesis technology spans more than 20 years. He’s developed a thriving business selling ...