The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs.
As system-on-chip (SoC) designs evolve, they aren’t just getting bigger — they’re becoming more intricate. One of the trickiest challenges in this evolution lies in handling resets. Today’s ...
The 74HC73 is a dual JK flip-flop with reset and negative edge trigger. This device features individual J, K, clock (nCP) and reset (nR) inputs; also complementary nQ and nQ outputs. It complies with ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results